The present disclosure relates generally to computer processors, and more specifically, to checkpoints for a simultaneous multithreading (SMT) processor cores.
Simultaneous multithreading allows various core resources of a processor to be shared by a plurality of instruction streams known as threads. Core resources can include instruction-execution units, caches, translation-lookaside buffers (TLBs), and the like, which may be collectively referred to generally as a processor core or simply a core. A single thread whose instructions access data may not fully utilize the core resources due to the latency to resolve data located in a memory nest. Multiple threads accessing data sharing a core resource typically result in a higher core utilization and core instruction throughput, but individual threads may experience slower execution. In a super-scalar processor simultaneous multithreading (SMT) implementation, multiple threads may be simultaneously serviced by the core resources of one or more cores. Management of multiple threads can also consume resources, as additional processing cycles may be needed to maintain program order and provide recovery features in case of a fault.